As the complexity and data processing speeds of electronic products continue to increase, the properties of the interconnecting circuitry which connects complex and high speed integrated circuit devices become more pronounced and must be carefully analyzed to ensure reliable circuit performance. Often, it is the increases in complexity and data processing speeds of integrated circuit devices that dictate performance improvements in the interconnecting circuitry to which the devices are mounted.
For example, the complexity of integrated circuit devices, and in particular the advent of surface mount technologies, dictate that greater densities of signal traces be packed into smaller packages to reduce costs and improve reliability. Signal trace widths and spacing has decreased to accommodate higher densities. Moreover, greater densities may be obtained with double-sided and multilayer printed wiring boards having multiple conductive layers that are typically electrically connected via conductive through holes.
Printed wiring boards typically include a number of high density areas in which electronic circuitry is located. In each of the high density areas, there is typically an associated high density of interconnections. Other areas of the circuit board typically require only relatively low electronic wiring densities for providing interconnection for connectors, discrete components, low pin count semiconductor devices and the like. However, conventional techniques of manufacturing printed wiring boards typically involve the production of individual layers of electronic circuitry of varying densities, of a single size. Upon production, the layers are aligned and laminated together to produce a multilayer board of the same size. These completed multilayer boards are then tested. If any portion of the multilayer board does not meet testing requirements or simply fails, the entire board has to be discarded.
Examples of such conventional techniques of manufacturing printed wiring boards are described in U.S. Pat. Nos. 5,401,909 and 5,582,745. Each of these patents describe printed circuit assemblies and associated methods of manufacture in which very high density circuitry is provided in regions where external components are to be directly attached. These patents describe the build up of a single layers of dielectric and metallization on the entire board and subsequently etching selected areas to provide various high density regions. Such a technique however, only provides for a single layer of electronic interconnection using complex build up technology with relatively low yield. In addition, as discussed earlier, should any portion of the resulting printed circuit assembly fail, the entire board has to be discarded.
Moreover, with the increasing integration density of semiconductor components such as microprocessors or logic chips, there is a proportional increase in the number and density of connecting input/output terminals on the chips. addition, the requirements on critical signal delay times within data processing systems have demanded increasingly shorter minimum distances between critical chips. To accommodate this demand, the dimensions of electronic wiring on the printed wiring board have decreased to provide a corresponding increase in wiring density.
However, with such decrease in the dimensions of electronic wiring on the printed wiring board, the difficulty of manufacture increases, as does the difficulty of testing. Accordingly, it is becoming increasingly expensive to manufacture and to test multilayer boards with varying densities using conventional techniques.
Accordingly, there is a need in the technology for manufacturing a printed wiring assembly in which localized high density modules or nodes of density may be separately and individually manufactured and tested prior to alignment and attachment of the modules or nodes to a printed wiring board.